1. Field of the Invention
The present-invention relates to a semiconductor device in which memory cells and peripheral circuits (core) thereof are provided on the same substrate; and a method for fabricating such a device. More particularly, the present invention relates to a semiconductor device having a reduced area occupied by the core section and an improved operating speed; and a method for fabricating such a device.
2. Description of the Related Art
In recent years, the degree of integration of a semiconductor device has been increased. In a system-on-chip (SOC) device, memory cells and peripheral circuits (core) such as a central processing unit (CPU) for controlling the operation of the memory cells are formed on the same substrate. In such a SOC device, the memory cells are required to stably maintain data therein even when an xcex1 ray is incident thereon, i.e., to have a soft error resistance, and the core is required to increase the operating speed of logical circuits thereof. Therefore, in the case where the memory cells form an SRAM (static random access memory), it is necessary to increase the source-drain junction capacitance of each CMOS (complementary metal-oxide semiconductor) transistor in the SRAM section, while decreasing the source-drain junction capacitance of each CMOS transistor in the core section.
However, the following problems arise when an impurity concentration of a well of each circuit in the core section is reduced in order to reduce the junction capacitance in the core section. Each of FIG. 1A and FIG. 1B shows a cross-sectional view illustrating punch-through occurring under a device separation region in a conventional CMOS transistor. As shown in FIG. 1A and FIG. 1B, in the CMOS transistor, a p-well 83 and an n-well 84 are provided on the surface of a semiconductor substrate 81 and separated from each other by a device separation film 82. The CMOS transistor includes an n-channel MOS transistor 87 and a p-channel MOS transistor 88. The n-channel MOS transistor 87 includes an n+-source diffusion layer 85a and an n+-drain diffusion layer 85b provided at the surface of the p-well 83. The p-channel MOS transistor 88 includes a p+-source diffusion layer 86a and a p+-drain diffusion layer 86b provided at the surface of the n-well 84.
Moreover, a p+-well contact layer 91 isolated from the n+-source diffusion layer 85a by an insulating film 89 is provided at the surface of the p-well 83, and an n+-well contact layer 92 isolated from the p+-source diffusion layer 86a by an insulating film 90 is provided at the surface of the n-well 84.
In the thus-structured CMOS transistor, when 0(V) is applied-to gate electrodes 93 and 94, 1.8(V) to the n+-drain diffusion layer 85b and the p+-drain diffusion layer 86b, 0(V) to the n+-source diffusion layer 85a and the p+-well contact layer 91, and 1.8(V) to the p+-source diffusion layer 86a and the n+-well contact layer 92, as shown in FIG. 1A, punch-through between the p+-drain diffusion layer 86b and the p+-well contact layer 91 is likely to occur under the device separation film 82 and the insulating film 89 via the n-well 84 and the p-well 83.
When 1.8(V) is applied to the gate electrodes 93 and 94, 0(V) to the n+-drain diffusion layer 85b and the p+-drain diffusion layer 86b, 0(V) to the n+-source diffusion layer 85a and the p+-well contact layer 91, and 1.8(V) to the p+-source diffusion layer 86a and the n+-well contact layer 92, as shown in FIG. 1B, punch-through between the n+-well contact layer 92 and the n+-drain diffusion layer 85b is likely to occur under the device separation film 82 and the insulating film 90 via the n-well 84 and the p-well 83. Hereinafter, such punch-through is referred to as xe2x80x9cwell-to-well punch-throughxe2x80x9d.
When the impurity concentration of an area, e.g., a well, near the area where the source-drain diffusion layer of the CMOS transistor is to be formed is reduced in order to reduce the junction capacitance, punch-through is more likely to occur under the device separation region.
Conventionally, the above-described problem has been addressed as follows. In the core section, the impurity concentration of the well is reduced while increasing the width of the device separation film disposed between the pMOS and the nMOS which together form the CMOS. FIG. 2A and FIG. 2B through FIG. 12A and FIG. 12B show cross-sectional views sequentially illustrating the steps of a conventional method for fabricating a semiconductor device. In these figures, each of FIG. 2A through FIG. 12A shows a region corresponding the core section of the semiconductor device, and each of FIG. 2B through FIG. 12B shows a region corresponding to the SRAM section of the semiconductor device.
First, as shown in FIG. 2A and FIG. 2B, a pxe2x88x92-epitaxial layer 52 is formed on a p-type silicon substrate 51 in both of the core section and the SRAM section. Next, in the core section, a device separation film 53a is formed in a predetermined area at the surface of the pxe2x88x92-epitaxial layer 52, and in the SRAM section, a device separation film 53b is formed in a predetermined area at the surface of the pxe2x88x92-epitaxial layer 52. As a result, the core section is defined into an nMOS region 111 where an n-channel MOS transistor is to be formed, and a pMOS region 112 where a p-channel MOS transistor is to be formed. The SRAM section is defined into an nMOS region 113 where an n-channel MOS transistor is to be formed, and a pMOS region 114 where a p-channel MOS transistor is to be formed. The width of the device separation film 53a is, for example, 1.2 xcexcm, and the width of the device separation film 53b is, for example, 0.4 xcexcm. Thereafter, a sacrificial oxide film (not shown) is formed over the entire surface of the device.
Next, as shown in FIG. 3A and FIG. 3B, a resist 54 including an opening 54a is formed. The opening 54a extends over the nMOS region 111 and a part of the device separation film 53a which is closer to the nMOS region 111, and the resist 54 completely covers the SRAM section. The size of a portion of the opening 54a which is located over the device separation film 53a is about a half of the size of the device separation film 53a. Next, B+ ions are implanted using the resist 54 as a mask with an acceleration voltage of 300 keV and a dose of 1.5xc3x971013, for example. Thus, in the core section, a p-type well 55 which is deeper than the device separation film 53a is formed in the pxe2x88x92-epitaxial layer 52.
As shown in FIG. 4A and FIG. 4B, a resist 56 including an opening 56a is formed after removing the resist 54. The opening 56a is provided in the center of the nMOS region 111, and the resist 56 completely covers the SRAM section. Next, B+ ions are implanted using the resist 56 as a mask with an acceleration voltage of 30 keV and a dose of 8xc3x971012, for example, so as to form a p-type channel 57 at an intermediate depth of the pxe2x88x92-epitaxial layer 52.
As shown in FIG. 5A and FIG. 5B, a resist 58 including an opening 58a is formed after removing the resist 56. The opening 58a extends over the nMOS region 113 and a part of the device separation film 53b which is closer to the nMOS region 113, and the resist 58 completely covers the core section. Next, in the SRAM section, B+ ions are implanted using the resist 58 as a mask, for example, with an acceleration voltage of 150 keV and a dose of 2xc3x971013, so as to form a p-type well 59 in the pxe2x88x92-epitaxial layer 52. Moreover, B+ ions are implanted using the resist 58 as a mask, for example, with an acceleration voltage of 30 keV and a dose of 1.5xc3x971013, so as to form a p-type channel 60 in the p-type well 59.
As shown in FIG. 6A and FIG. 6B, a resist 61 including an opening 61a is formed after removing the resist 58. The opening 61a extends over the pMOS region 112 and a part of the device separation film 53a which is closer to the pMOS region 112, and the resist 61 completely covers the SRAM section. Next, in the core section, P+ ions are implanted using the resist 61 as a mask with an acceleration voltage of 600 keV and a dose of 1.5xc3x971013, for example, so as to form an n-type well 62 in the pxe2x88x92-epitaxial layer 52.
As shown in FIG. 7A and FIG. 7B, a resist 63 including an opening 63a is formed after removing the resist 61. The opening 63a is provided in the center of the pMOS region 112, and the resist 63 completely covers the SRAM section. Next, in the core section, As+ ions are implanted using the resist 63 as a mask, for example, with an acceleration voltage of 100 keV and a dose of 3xc3x971012, so as to form an n-type channel 64 at an intermediate depth of the n-type well 62.
As shown in FIG. 8A and FIG. 8B, a resist 65 including an opening 65a is formed after removing the resist 63. The opening 65a extends over the pMOS region 114 and a part of the device separation film 53b which is closer to the pMOS region 114, and the resist 65 completely covers the core section. Next, in the SRAM section, P+ ions are implanted using the resist 65 as a mask, for example, with an acceleration voltage of 350 keV and a dose of 2xc3x971013, so as to form an n-type well 66 in the pxe2x88x92-epitaxial layer 52. Furthermore, As+ ions are implanted, for example, with an acceleration voltage of 100 keV and a dose of 1.4xc3x971013, so as to form an n-type channel 67 at an intermediate depth of the n-type well 66.
As shown in FIG. 9A and FIG. 9B, after removing the resist 65, a gate oxide film 68 and a gate electrode 69 are formed in each of the nMOS region 111, the pMOS region 112, the nMOS region 113, and the pMOS region 114.
Next, as shown in FIG. 10A and FIG. 10B, side walls 70 are formed at both sides of the gate oxide film 68 and the gate electrode 69.
Next, as shown in FIG. 11A and FIG. 11B, a resist 71 including openings 71a and 71b is formed. The openings 71a and 71b extend over the nMOS regions 111 and 113, respectively. Next, As+ ions are implanted using the resist 71 as a mask, for example, with an acceleration voltage of 20 keV and a dose of 5xc3x971015, so as to form an n+-source-drain diffusion layer 72 in each of the nMOS region 111 and the nMOS region 113.
After removing the resist 71, as shown in FIG. 12A and FIG. 12B, a resist 73 including openings 73a and 73b is formed. The openings 73a and 73b extend over the pMOS regions 112 and 114, respectively. Next, B+ ions are implanted using the resist 73 as a mask, for example, with an acceleration voltage of 4 keV and a dose of 5xc3x971015, so as to form a p30 -source-drain diffusion layer 74 in each of the pMOS regions 112 and 114.
Thereafter, the implanted ions are activated by means of annealing. Then, wiring or the like is provided so as to complete the semiconductor device.
In order to prevent punch-through under the device separation region, a semiconductor device including a region with a high impurity concentration down below the device separation film has been proposed (Japanese Patent Laid-Open Publication No.8-97378). According to the semiconductor device described in this publication, within a well in which a MOS transistor is formed, a high impurity concentration region is provided so as to extend below a device separation film formed around the transistor.
In a SOC device, however, when an area occupied by the memory cell section (SRAM section) is compared to an area occupied by the core section, the area occupied by the core section is significantly larger than that occupied by the memory cell section. Moreover, in the semiconductor device fabricated according to the conventional method illustrated in FIG. 1A through FIG. 12B, the device separation film 53a has a wide width in the core section. As a result, such problem as a large chip area arises.
Furthermore, according to the semiconductor device disclosed in Japanese Patent Laid-Open Publication No.8-97378, a high impurity concentration region exists below the MOS transistor, thereby influencing a threshold voltage of the MOS transistor. As the degree of integration of the semiconductor device increases, such influence becomes more prominent. In addition, this publication does not contemplate the use of the technique in a SOC device. When this technique is used in a SOC device, the number of production steps may increase. Furthermore, when this technique is used in the core section of a SOC device, the junction capacitance may increase due to the high impurity concentration region, thereby reducing the operating speed.
While these problems are prominent in SOC devices, similar problems will arise in a memory chip itself, considering the peripheral region, e.g., a decoder, as being equivalent to the core section.
An object of the present invention is to provide a semiconductor device capable of realizing a high-speed operation of a core section where logical circuits are formed, reducing an area occupied by the core section, and preventing punch-through occurring under a device separation region in a CMOS; and a method for fabricating such a semiconductor device.
According to one aspect of the present invention, a semiconductor device comprises, a semiconductor substrate of a first conductivity type, a memory cell section complementary, transistor provided on the semiconductor substrate, and a core section complementary transistor provided on the semiconductor substrate. The core section complementary transistor has a first well of a second conductivity type provided in the semiconductor substrate, a first core section MOS transistor provided on the first well of the second conductivity type, a second core section MOS transistor provided on the semiconductor substrate a device separation film which separates the first core section MOS transistor and the second core section MOS transistor from each other, and a well of the first conductivity type provided under a part of the device separation film which is closer to the second core section MOS transistor. The first core section MOS transistor has source-drain regions of the first conductivity type. The second core section MOS transistor has source-drain regions of the second conductivity type. The well of the first conductivity type has an impurity concentration higher than that of the semiconductor substrate.
According to the aspect of the present invention, the well of the first conductivity type having an impurity concentration higher than that of the semiconductor substrate is provided in the core section under the part of the device separation film which is closer to the second core section MOS transistor, thereby improving punch-through resistance under the device separation region. As a result, the width of the device separation film in the core section may be reduced, thereby reducing the area occupied by the core section. Moreover, since the second core section MOS transistor is provided on the semiconductor substrate, the junction capacitance thereof is smaller than that of a conventional MOS transistor which is provided on a well. As a result, a high-speed operation is realized.
It is preferable to have a third well of the second conductivity type provided under a part of the device separation film which is closer to the first core section MOS transistor, wherein an impurity concentration of the third well of the second conductivity type is higher than that of the first well of the second conductivity type. In such a case, the impurity concentration of the second well of the second conductivity type may be substantially equal to that of the third well of the second conductivity type. By providing the third well of the second conductivity type, punch-through resistance under the device separation film is further increased, thereby further reducing the area occupied by the core section.
According to another aspect of the present invention, a method for fabricating a semiconductor device comprises the step of forming a core section complementary transistor and a memory cell section complementary transistor on a semiconductor substrate of a first conductivity type. The forming complementary transistors has forming a first device separation film and a second device separation film on the semiconductor substrate, wherein the first device separation film separates a first core section MOS transistor and a second core section MOS transistor from each other, and the second device separation film separates a first memory cell section MOS transistor and a second memory cell section MOS transistor from each other. The first and second core section MOS transistors constitute the core section complementary transistor. The first and second memory cell section MOS transistors constitute the memory cell section complementary transistor. Each of the first core section MOS transistor and the first memory cell section MOS transistor includes source-drain regions of the first conductivity type. The each of the second core section MOS transistor and the second memory cell section MOS transistor includes source-drain regions of s second conductivity type.
According to the aspect of the present invention, the first well of the first conductivity type and the second well of the first conductivity type are simultaneously formed. As a result, punch-through resistance under the device separation film may be increased without increasing the number of the fabrication steps.
It should be noted that, by implanting the ions of the first conductivity type at a low dose after the ions of the second conductivity type are implanted, the effective impurity concentration of the well in the first core section MOS transistor is reduced, thereby reducing the junction capacitance thereof. As a result, a high-speed operation is realized.